Integrated memory devices, in particular semiconductor memories, can be classified based on the storage duration of stored information. Volatile semiconductor memories such as DRAMs (Dynamic Random Access Memories), for example, have memory cells that store written information only for fractions of seconds and therefore must be repeatedly refreshed. In nonvolatile semiconductor memories, by contrast, stored information is retained over a long period of time, typically over several years, even after the power supply has been switched off.
A particularly space-saving arrangement of memory cells is achieved in the case of such semiconductor memories whose memory cells have layer stacks at crossover locations between first lines (for example bit lines) and second lines (for example word lines), the non-reactive resistance of which layer stacks can be altered by applying suitable voltages directly via the first and second lines to which the layer stack extends. Memory cells formed in this way do not require a selection transistor. A memory cell array having such memory cells is referred to as a “cross-point array”. The basic substrate area required per memory cell in the case of a “cross-point array” results from the pitch of the bit lines and the word lines, so that a cross-point array has a very high memory cell density.
Such a memory cell array has memory cells whose non-reactive resistance has a high value or a low value depending on the programming state. In either case, along the layer stacks, leakage currents arise between the first and second lines to which the layer stacks are connected. Each individual layer stack enables a leakage current between that first line and that second line to which the layer stack extends (and the memory cell is thus connected). In the case of a memory cell programmed in a high-resistance state, its leakage current contribution is usually negligible. Problems exist, however, in the case of those memory cells that are in a low-resistance memory state. Larger leakage currents flow along the layer stacks of such memory cells and, in view of the high number of memory cells per word line or per bit line, may produce considerable leakage current contributions along the lines. Particularly when the total of memory cells programmed in a low-resistance state which are connected along one and the same line is very large, an electrical potential applied to one end of the relevant line may vary (for example decrease) considerably along the course of the line, with the result that a reliable biasing of the entire line becomes all the more difficult, the more memory cells are connected to the respective line. The more memory cells are connected to a word line or bit line and the longer the corresponding line thus is, the more difficult it is to be able to guarantee that a predefined electrical potential will be complied with over the entire interconnect length.
Since memory devices formed as cross-point arrays, for example solid-electrolyte memory devices, are operationally reliable only when predefined bit line and word line potentials are ensured with arbitrary data patterns stored in a memory cell array, the permissible interconnect length (measured in the number of memory cells per line) up to which such a memory device can still be operated reliably is limited. The maximum permissible number, for functionally reliable operation, of memory cells that are programmed in a low-resistance state and are connected to the same line conventionally prescribes the maximum permissible interconnect length of such lines, since memory devices formed as cross-point arrays must function reliably even when the entire memory cell array is occupied with data values corresponding to a memory state programmed in a low-resistance state.